With increases in the packing density of semiconductor memories, a capacitor element with larger capacity is needed. Therefore, a technology to integrate a capacitor element including a dielectric layer with high dielectric constant or a ferroelectric characteristics into a integrated circuit lately has attracted considerable attention.
In order to put a nonvolatile RAM into practice which enables writing and reading with lower operating voltage at higher speed compared to conventional devices, a technology to integrate a capacitor element including a ferroelectric layer has been pursued.
A conventional method for manufacturing a semiconductor device including a dielectric with high dielectric constant or a ferroelectric characteristics (hereinafter, a dielectric with high dielectric) is explained below referring to FIGS. 20A and 20B.
As shown in FIG. 20A, a first metal film 202 (e.g. a Pt film) is formed on a substrate 201 with an integrated circuit by sputtering. A dielectric film 203 with high dielectric constant is formed on the first metal film 202 by spin coating or chemical vapor deposition (CVD), followed by forming a second metal film 204 (e.g. a Pt film) on the dielectric film 203 by sputtering. After a photoresist 209 is formed on the second metal film 204 in a predetermined pattern, each film is selectively removed by dry etching to form a capacitor element 208 composed of first electrode 205, a capacitor dielectric layer 206 and a second electrode 207.
However, in such a capacitor element produced by the conventional method, a capacitor dielectric layer with high dielectric constant is degraded in electric characteristics. Such a degradation also is observed in a transistor including a dielectric layer with high dielectric constant.